Publications
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Conference and Journal Papers
2021
C. Kumar, A. Seshadri, A. Chaudhary, S. Bhawalkar, R. Singh, and E. Rotenberg. Post-Fabrication Microarchitecture. Proceedings of the 54th IEEE/ACM International Symposium on Microarchitecture (MICRO-54), pp. ?-?, October 2021. (to appear) [pdf]
2020
V. Srinivasan, R. Basu Roy Chowdhury, and E. Rotenberg. Slipstream Processors Revisited: Exploiting Branch Sets. Proceedings of the 47th ACM/IEEE International Symposium on Computer Architecture (ISCA-47), pp. 105-117, May 2020. [pdf]
C. Kumar, A. Chaudhary, S. Bhawalkar, U. Mathur, S. Jain, A. Vastrad, and E. Rotenberg. Post-Silicon Microarchitecture. IEEE Computer Architecture Letters (CAL), 19(1):26-29, Jan.-June 1, 2020. (Date of Publication: 09 March 2020.) [pdf]
2017
V. Srinivasan, R. Basu Roy Chowdhury, E. Forbes, R. Widialaksono, Z. Zhang, J. Schabel, S. Ku, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon. H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor. Proceedings of the 35th IEEE International Conference on Computer Design (ICCD-35), pp. 145-152, November 2017. [pdf]
S. Ku, E. Forbes, R. Basu Roy Chowdhury, and E. Rotenberg. A Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures. Proceedings of the 18th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 131-137, March 2017. [pdf]
2016
R. Widialaksono, R. Basu Roy Chowdhury, Z. Zhang, J. Schabel, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon. Physical Design of a 3D-stacked Heterogeneous Multi-Core Processor. Proceedings of the 2016 IEEE International 3D Systems Integration Conference (3DIC’16), pp. 1-5, November 2016. [pdf]
E. Forbes and E. Rotenberg. Fast Register Consolidation and Migration for Heterogeneous Multi-core Processors. Proceedings of the 34th IEEE International Conference on Computer Design (ICCD-34), pp. 1-8, October 2016. [pdf]
Best Paper Award in the Processor Architecture Track
R. Basu Roy Chowdhury, A. K. Kannepalli, S. Ku, and E. Rotenberg. AnyCore: A Synthesizable RTL Model for Exploring and Fabricating Adaptive Superscalar Cores. Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’16), pp. 214-224, April 2016. [pdf]
2015
To see what’s new with our processor prototyping efforts, please jump to the workshop and poster sections:
- Experiences with Two FabScalar-based Chips. 6th Workshop on Architectural Research Prototyping (WARP’15), June 14, 2015.
- FabScalar-RISC-V. 2nd RISC-V Workshop, June 29-30, 2015.
- Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor. Poster session of Hot Chips 2015, August 23-25, 2015.
2014
R. Sheikh, J. Tuck, and E. Rotenberg. Control-Flow Decoupling: An Approach for Timely, Non-speculative Branching. IEEE Transactions on Computers, 64(8):2182-2203, publication date (preprint): October 2014, issue date: August 2015. [pdf]
E. Forbes, N. K. Choudhary, B. H. Dwiel, and E. Rotenberg. Design-Effort Alloy: Boosting a Highly Tuned Primary Core with Untuned Alternate Cores. Proceedings of the 32nd IEEE International Conference on Computer Design (ICCD-32), pp. 408-415, October 2014. [pdf]
T. Nakabayashi, T. Sugiyama, T. Sasaki, E. Rotenberg, and T. Kondo. Co-simulation Framework for Streamlining Microprocessor Development on Standard ASIC Design Flow. Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC-19), pp. 400-405, January 2014. [pdf]
2013
E. Rotenberg, B. H. Dwiel, E. Forbes, Z. Zhang, R. Widialaksono, R. Basu Roy Chowdhury, N. Tshibangu, S. Lipa, W. R. Davis, and P. D. Franzon. Rationale for a 3D Heterogeneous Multi-core Processor. Proceedings of the 31st IEEE International Conference on Computer Design (ICCD-31), pp. 154-168, October 2013. [pdf]
S. Navada, N. K. Choudhary, S. V. Wadhavkar, and E. Rotenberg. A Unified View of Non-monotonic Core Selection and Application Steering in Heterogeneous Chip Multiprocessors. Proceedings of the 22nd IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT-22), pp. 133-144, September 2013. [pdf]
S. Priyadarshi, N. K. Choudhary, B. Dwiel, A. Upreti, E. Rotenberg, R. Davis, and P. Franzon. Hetero2 3D Integration: A Scheme for Optimizing Efficiency/Cost of Chip Multiprocessors. Proceedings of the 14th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 1-7, March 2013. [pdf]
2012
R. Sheikh, J. Tuck, and E. Rotenberg. Control-Flow Decoupling. Proceedings of the 45th IEEE/ACM International Symposium on Microarchitecture (MICRO-45), pp. 329-340, December 2012. [pdf]
N. K. Choudhary, B. H. Dwiel, and E. Rotenberg. A Physical Design Study of FabScalar-generated Superscalar Cores. Proceedings of the 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 165-170, October 2012. [pdf]
N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi, and E. Rotenberg. FabScalar: Automating Superscalar Core Design. IEEE Micro, Special Issue: Micro’s Top Picks from the Computer Architecture Conferences, 32(3):48-59, May-June 2012. [pdf]
T. Nakabayashi, T. Sasaki, E. Rotenberg, K. Ohno and T. Kondo. Research for Transporting Alpha ISA and Adopting Multi-processor to FabScalar. Proceedings of the Symposium on Advanced Computing Systems and Infrastructures 2012 (SACSIS2012), pp. 374-381, May 2012. (in Japanese)
B. H. Dwiel, N. K. Choudhary, and E. Rotenberg. FPGA Modeling of Diverse Superscalar Processors. Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’12), pp. 188-199, April 2012. [pdf]
2011
N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi, and E. Rotenberg. FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template. Proceedings of the 38th IEEE/ACM International Symposium on Computer Architecture (ISCA-38), pp. 11-22, June 2011. [pdf]
2010
S. Navada, N. K. Choudhary, and E. Rotenberg. Criticality-driven Superscalar Design Space Exploration. Proceedings of the 19th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT-19), pp. 261-272, September 2010. [pdf]
M. Al-Otoom, E. Forbes, and E. Rotenberg. EXACT: Explicit Dynamic-Branch Prediction with Active Updates. Proceedings of the 7th ACM International Conference on Computing Frontiers (CF-7), pp. 165-176, May 2010. [pdf]
2009
H. Hashemi Najaf-abadi and E. Rotenberg. The Importance of Accurate Task Arrival Characterization in the Design of Processing Cores. Proceedings of the 2009 IEEE International Symposium on Workload Characterization (IISWC’09), pp. 75-85, October 2009. [pdf]
H. Hashemi Najaf-abadi, N. K. Choudhary, and E. Rotenberg. Core-Selectability in Chip Multiprocessors. Proceedings of the 18th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT-18), pp. 113-122, September 2009. [pdf]
H. Hashemi Najaf-abadi and E. Rotenberg. Architectural Contesting. Proceedings of the 15th IEEE International Symposium on High-Performance Computer Architecture (HPCA-15), pp. 189-200, February 2009. [pdf]
2008
V. K. Reddy and E. Rotenberg. Coverage of a Microarchitecture-level Fault Check Regimen in a Superscalar Processor. Proceedings of the 38th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-38, DCCS track), pp. 1-10, June 2008. [pdf]
H. Hashemi Najaf-abadi and E. Rotenberg. Configurational Workload Characterization. Proceedings of the 2008 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’08), pp. 147-156, April 2008. [pdf]
2007
V. K. Reddy and E. Rotenberg. Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. Proceedings of the 37th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-37, DCCS track), pp. 307-316, June 2007. [pdf]
A. S. Al-Zawawi, V. K. Reddy, E. Rotenberg, and H. Akkary. Transparent Control Independence (TCI). Proceedings of the 34th IEEE/ACM International Symposium on Computer Architecture (ISCA-34), pp. 448-459, June 2007. [pdf]
R. K. Venkatesan, A. S. AL-Zawawi, K. Siva, and E. Rotenberg. ZettaRAMTM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. IEEE Transactions on Computers, Special Section on Nano Systems and Computing, 56(2):147-160, February 2007. [pdf]
* The ZettaRAMTM mark is a trademark of ZettaCore Inc.
* The ZettaCoreTM mark is a trademark of ZettaCore Inc.
2006
V. K. Reddy, S. Parthasarathy, and E. Rotenberg. Understanding Prediction-Based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance. Proceedings of the 12th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), pp. 83-94, October 2006. [pdf]
V. K. Reddy, A. S. Al-Zawawi, and E. Rotenberg. Assertion-Based Microarchitecture Design for Improved Fault Tolerance. Proceedings of the 24th IEEE International Conference on Computer Design (ICCD-24), pp. 362-369, October 2006. [pdf]
E. Rotenberg and R. K. Venkatesan. The State of ZettaRAM. Proceedings of the 1st IEEE International Conference on Nano-Networks, pp. 1-5, September 2006. [pdf]
R. K. Venkatesan, S. Herr, and E. Rotenberg. Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM. Proceedings of the 12th IEEE International Symposium on High-Performance Computer Architecture (HPCA-12), pp. 157-167, February 2006. [pdf]
K. Seth, A. Anantaraman, F. Mueller, and E. Rotenberg. FAST: Frequency-Aware Static Timing Analysis. ACM Transactions on Embedded Computing Systems (TECS), 5(1):200-224, February 2006.
A. Anantaraman and E. Rotenberg. Non-Uniform Program Analysis & Repeatable Execution Constraints: Exploiting Out-of-Order Processors in Real-Time Systems. ACM SIGBED Review, Volume 3, Number 1, January 2006. [pdf]
2005
A. El-Haj-Mahmoud, A. S. AL-Zawawi, A. Anantaraman, and E. Rotenberg. Virtual Multiprocessor: An Analyzable, High-Performance Microarchitecture for Real-Time Computing. Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’05), pp. 213-224, September 2005. [pdf]
R. K. Venkatesan, A. S. AL-Zawawi, and E. Rotenberg. Tapping ZettaRAMTM for Low-Power Memory Systems. Proceedings of the 11th IEEE International Symposium on High-Performance Computer Architecture (HPCA-11), pp. 83-94, February 2005. [pdf]
* The ZettaRAMTM mark is a trademark of ZettaCore Inc.
* The ZettaCoreTM mark is a trademark of ZettaCore Inc.
2004
A. Anantaraman, K. Seth, E. Rotenberg, and F. Mueller. Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). Proceedings of the 25th IEEE International Real-Time Systems Symposium (RTSS-25), pp. 114-125, December 2004. [pdf]
A. El-Haj-Mahmoud and E. Rotenberg. Safely Exploiting Multithreaded Processors to Tolerate Memory Latency in Real-Time Systems. Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’04), pp. 2-13, September 2004. [pdf]
J. J. Koppanalil and E. Rotenberg. A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. IEEE Transactions on Computers, 53(4):399-413, April 2004.
2003
K. Seth, A. Anantaraman, F. Mueller, and E. Rotenberg. FAST: Frequency-Aware Static Timing Analysis. Proceedings of the 24th IEEE International Real-Time Systems Symposium (RTSS-24), pp. 40-51, December 2003.
H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte. Adaptive Mode Control: A Static-Power-Efficient Cache Design. ACM Transactions on Embedded Computing Systems (TECS), Special issue on power-aware embedded computing, 2(3):347-372, August 2003.
A. Anantaraman, K. Seth, K. Patil, E. Rotenberg, and F. Mueller. Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. Proceedings of the 30th IEEE/ACM International Symposium on Computer Architecture (ISCA-30), pp. 350-361, June 2003. [pdf]
K. Z. Ibrahim, G. T. Byrd, and E. Rotenberg. Slipstream Execution Mode for CMP-Based Multiprocessors. Proceedings of the 9th IEEE International Symposium on High-Performance Computer Architecture (HPCA-9), pp. 179-190, February 2003. [pdf]
2002
J. Koppanalil, P. Ramrakhyani, S. Desai, A. Vaidyanathan, and E. Rotenberg. A Case for Dynamic Pipeline Scaling. Proceedings of the 5th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’02), pp. 1-8, October 2002. [pdf]
A. R. Lebeck, J. J. Koppanalil, T. Li, J. Patwardhan, and E. Rotenberg. A Large, Fast Instruction Window for Tolerating Cache Misses. Proceedings of the 29th IEEE/ACM International Symposium on Computer Architecture (ISCA-29), pp. 59-70, May 2002. [pdf]
2001
E. Rotenberg. Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems. Proceedings of the 34th IEEE/ACM International Symposium on Microarchitecture (MICRO-34), pp. 28-39, December 2001. [pdf]
H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte. Adaptive Mode Control: A Static-Power-Efficient Cache Design. Proceedings of the 10th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT’01), pp. 61-70, September 2001. [pdf]
2000
Z. Purser, K. Sundaramoorthy, and E. Rotenberg. A Study of Slipstream Processors. Proceedings of the 33rd IEEE/ACM International Symposium on Microarchitecture (MICRO-33), pp. 269-280, December 2000. [pdf]
K. Sundaramoorthy, Z. Purser, and E. Rotenberg. Slipstream Processors: Improving both Performance and Fault Tolerance. Proceedings of the 9th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-9), pp. 257-268, November 2000. [pdf]
Eric Rotenberg and James E. Smith. Control Independence in Trace Processors. Journal of Instruction-Level Parallelism (JILP), Special issue – papers from MICRO-32, vol. 2, pp. 63-85, May 2000. [pdf]
1999
Eric Rotenberg and James E. Smith. Control Independence in Trace Processors. Proceedings of the 32nd IEEE/ACM International Symposium on Microarchitecture (MICRO-32), pp. 4-15, November 1999. [pdf]
Eric Rotenberg. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. Proceedings of the 29th IEEE International Symposium on Fault-Tolerant Computing (FTCS-29), pp. 84-91, June 1999. [pdf]
Eric Rotenberg, Steve Bennett, and James E. Smith. A Trace Cache Microarchitecture and Evaluation. IEEE Transactions on Computers, Special Issue on Cache Memory, 48(2):111-120, February 1999. [pdf]
Eric Rotenberg, Quinn Jacobson, and James E. Smith. A Study of Control Independence in Superscalar Processors. Proceedings of the 5th IEEE International Symposium on High-Performance Computer Architecture (HPCA-5), pp. 115-124, January 1999. [pdf]
Also see detailed Technical Report.
1997
Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, and James E. Smith. Trace Processors. Proceedings of the 30th IEEE/ACM International Symposium on Microarchitecture (MICRO-30), pp. 138-148, December 1997. [pdf]
Quinn Jacobson, Eric Rotenberg, and James E. Smith. Path-Based Next Trace Prediction. Proceedings of the 30th IEEE/ACM International Symposium on Microarchitecture (MICRO-30), pp. 14-23, December 1997. [pdf]
1996
Erik Jacobsen, Eric Rotenberg, and James E. Smith. Assigning Confidence to Conditional Branch Predictions. Proceedings of the 29th IEEE/ACM International Symposium on Microarchitecture (MICRO-29), pp. 142-152, December 1996. [pdf]
Eric Rotenberg, Steve Bennett, and James E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. Proceedings of the 29th IEEE/ACM International Symposium on Microarchitecture (MICRO-29), pp. 24-34, December 1996. [pdf]
Also see detailed Technical Report.
Workshop Papers and Presentations
R. Basu Roy Chowdhury, A. K. Kannepalli, and E. Rotenberg. FabScalar-RISC-V. 2nd RISC-V Workshop, June 29-30, 2015. [presentation (pdf)]
E. Forbes, R. Basu Roy Chowdhury, B. Dwiel, A. Kannepalli, V. Srinivasan, Z. Zhang, R. Widialaksono, T. Belanger, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon. Experiences with Two FabScalar-based Chips. 6th Workshop on Architectural Research Prototyping (WARP’15), in conjunction with ISCA-42, June 14, 2015.
[paper (pdf), presentation (ppt)]
M. Al-Otoom, R. Sheikh, and E. Rotenberg. A Case for a Software-Managed Reconfigurable Branch Predictor. 5th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT’12), in conjunction with ISCA-39, June 2012. [pdf]
N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, S. S. Navada, H. Hashemi Najaf-abadi, and E. Rotenberg. FabScalar. 4th Workshop on Architectural Research Prototyping (WARP’09), in conjunction with ISCA-36, June 2009. [pdf]
H. Hashemi Najaf-abadi and E. Rotenberg. Exploiting Detachability: A Non-Silicon Approach to Polymorphism. 4th Workshop on Non-Silicon Computing (NSC-4), in conjunction with ISCA-34, June 2007.
H. Hashemi Najaf-abadi and E. Rotenberg. Architectural Contesting: Exposing and Exploiting Temperamental Behavior.
- Reconfigurable and Adaptive Architecture Workshop (RAAW), in conjunction with MICRO-39, December 2006.
- Also appears in ACM SIGARCH Computer Architecture News (CAN), 35(3):28-35, June 2007. [pdf ]
A. Anantaraman and E. Rotenberg. Non-Uniform Program Analysis & Repeatable Execution Constraints: Exploiting Out-of-Order Processors in Real-Time Systems. Work in Progress Session for the 26th IEEE International Real-Time Systems Symposium (RTSS-26), December 2005. [pdf]
Posters
R. Basu Roy Chowdhury, A. Kannepalli, and E. Rotenberg. AnyCore-1: A Comprehensively Adaptive 4-way Superscalar Processor. Poster session of Hot Chips 2016, August 21-23, 2016. [poster (pdf)]
S. Ku, E. Forbes, R. Basu Roy Chowdhury, and E. Rotenberg. A Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures. Poster session of the 2016 Design Automation Conference (DAC’16), June 7, 2016. [poster (pptx)]
E. Forbes, Z. Zhang, R. Widialaksono, B. Dwiel, R. Basu Roy Chowdhury, V. Srinivasan, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon. Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor. Poster session of Hot Chips 2015, August 23-25, 2015. [poster (pdf)]
Technical Reports
M. Dechene, J. E. Forbes, and E. Rotenberg. Multithreaded Instruction Sharing. Technical Report, Department of Electrical and Computer Engineering, North Carolina State University, December 2010. [pdf]
A. Anantaraman, K. Seth, E. Rotenberg, and F. Mueller. Exploiting VISA for Higher Concurrency in Safe Real-Time Systems. Technical Report TR-2004-15, Department of Computer Science, North Carolina State University, May 2004. [pdf]
Z. Purser, K. Sundaramoorthy, and E. Rotenberg. Slipstream Memory Hierarchies. Technical Report CESR-TR-02-3, Center for Embedded Systems Research, Department of Electrical and Computer Engineering, North Carolina State University, February 2002. [pdf]
K. Sundaramoorthy, Z. Purser, and E. Rotenberg. Multipath Execution on Chip Multiprocessors Enabled by Redundant Threads. Technical Report CESR-TR-01-2, Center for Embedded Systems Research, Department of Electrical and Computer Engineering, North Carolina State University, October 2001. [pdf]
Ashwini Sidhaye, Paul Steinmetz, Eric Rotenberg, David Barrow, and Domenico Arpaia. Collecting Memory Address Traces from an Ericsson Cell Phone and Estimating Cache Performance. Technical Report CESR-TR-01-1, Center for Embedded Systems Research, Department of Electrical and Computer Engineering, North Carolina State University, August 2001. [pdf]
Eric Rotenberg. Exploiting Large Ineffectual Instruction Sequences. Technical Report, North Carolina State University, November 1999. [pdf]
Eric Rotenberg, Quinn Jacobson, and James E. Smith. A Study of Control Independence in Superscalar Processors. University of Wisconsin – Madison Technical Report #1389, December 1998. [pdf]
Eric Rotenberg, Steve Bennett, and James E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. University of Wisconsin – Madison Technical Report #1310, April 1996. [pdf]
Book Chapters
E. Rotenberg. Trace Caches, in Speculative Execution in High Performance Computer Architectures. D. Kaeli and P.-C. Yew, Eds. CRC Press, 2005.
E. Rotenberg and A. Anantaraman. Architecture of Embedded Microprocessors, in Multiprocessor Systems-on-Chips. Ahmed Jerraya and Wayne Wolf, Eds. San Francisco, CA: Morgan Kaufmann Publishers, 2005, pp. 81-112.
E. Rotenberg. Trace Caching and Trace Processors, in The Computer Engineering Handbook. Vojin Oklobdzija, Ed. CRC Press, 2001, pp. 8-37 — 8-45.
Theses
Eric Rotenberg. Trace Processors: Exploiting Hierarchy and Speculation. Ph.D. Thesis, University of Wisconsin – Madison, August 1999. [pdf]
Student Theses
S. Bhawalkar. Custom Data Prefetchers Evaluated on a Post-Silicon-Microarchitecture-Enabled Superscalar Processor. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2020. [NCSU library: on-line thesis]
C. Kumar. Post-Silicon Microarchitecture. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2020. [NCSU library: on-line thesis]
V. Srinivasan. Slipstream Processors Revisited: Exploiting Branch Sets. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2019. [NCSU library: on-line thesis]
A. Vastrad. Verilog Design and Verification of an Application Specific Branch Predictor for astar Benchmark. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2019. [NCSU library: on-line thesis]
S. Jain. Application Specific Parallelization. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2019. [NCSU library: on-line thesis]
A. Chaudhary. Custom EXACT Branch Predictor for astar Benchmark. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2019. [NCSU library: on-line thesis]
U. Mathur. Post-Silicon Microarchitecture (PSM) Implementation of Checkpointed Early Load Retirement (CLEAR). M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2019. [NCSU library: on-line thesis]
S. Ku. Design for Competitive Automated Layout (DCAL) of Superscalar Processors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2017. [NCSU library: on-line thesis]
R. Basu Roy Chowdhury. AnyCore: Design, Fabrication, and Evaluation of Comprehensively Adaptive Superscalar Processors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, September 2016. [NCSU library: on-line thesis]
J. E. Forbes. Hardware Thread Migration for 3D Die-stacked Heterogeneous Multi-core Processors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2016. [NCSU library: on-line thesis]
V. Srinivasan. Phase II Implementation and Verification of the H3 Processor. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2015. [NCSU library: on-line thesis]
S. Janmejay. Preliminary Investigation of High Level Synthesis of a C++ Superscalar Processor Model. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2015. [NCSU library: on-line thesis]
A. K. Kannepalli. Chip Bringup of the AnyCore Adaptive Superscalar Core. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2015. [NCSU library: on-line thesis]
W. Galliher. Squashed Branch Reuse. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2015. [NCSU library: on-line thesis]
S. Sabharwal. Microarchitectural Implementation of the MIPS System Coprocessor in FabScalar-generated Superscalar Cores. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2013. [NCSU library: on-line thesis]
J. W. Bowman. Microarchitectural Implementation of a Reduced x86 ISA in FabScalar-generated Superscalar Cores. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2013. [NCSU library: on-line thesis]
R. Sheikh. Control-Flow Decoupling: An Approach for Timely, Non-speculative Branching. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, April 2013. [NCSU library: on-line thesis]
S. V. Wadhavkar. Architecting a Workload-agnostic Heterogeneous Multi-core Processor. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, September 2012. [NCSU library: on-line thesis]
A. V. Shastri. Microarchitectural Implementation of the MIPS Floating-point ISA in FabScalar-generated Superscalar Cores. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2012. [NCSU library: on-line thesis]
S. S. Navada. A Unified View of Core Selection and Application Steering in Heterogeneous Chip Multiprocessors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, June 2012. [NCSU library: on-line thesis]
N. K. Choudhary. FabScalar: Automating the Design of Superscalar Processors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2012. [NCSU library: on-line thesis]
B. H. Dwiel. FPGA Modeling of Diverse Superscalar Processors. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, November 2011. [NCSU library: on-line thesis]
H. Hashemi Najaf-abadi. Core-Selectable Chip Multiprocessor Design. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, December 2010. [NCSU library: on-line thesis]
M. M. Al-Otoom. EXACT: Explicit Dynamic-Branch Prediction with Active Updates. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2010. [NCSU library: on-line thesis]
S. Rajan Vijaya Kumar. RTL Design and Analysis of a Fault Check Regimen for Superscalar Processors. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2010. [NCSU library: on-line thesis]
J. Gandhi. FabFetch: A Synthesizable RTL Model of a Pipelined Instruction Fetch Unit for Superscalar Processors. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, June 2010. [NCSU library: on-line thesis]
H. Mayukh. FabIssue: Automatic RTL Generation of Issue Logic in Superscalar Processors for Core Customization. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, June 2010. [NCSU library: on-line thesis]
T. A. Shah. FabMem: A Multiported RAM and CAM Compiler for Superscalar Design Space Exploration. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2010. [NCSU library: on-line thesis]
N. K. Choudhary. A Synthesizable HDL Model for Out-of-Order Superscalar Processors. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2009. [NCSU library: on-line thesis]
J. E. Forbes. Characterization of Load Address Idioms with Implications for Address Prediction. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, December 2008. [NCSU library: on-line thesis]
V. K. Reddy. Exploiting Microarchitecture Insights for Efficient Fault Tolerance. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2007. [NCSU library: on-line thesis]
A. S. Al-Zawawi. Transparent Control Independence (TCI). Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2007. [NCSU library: on-line thesis]
R. K. Venkatesan. Power-Scalable Memory: Exploiting Typical Charge Retention in DRAM and Charge-Voltage Decoupling in ZettaRAM. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2006. [NCSU library: on-line thesis]
M. M. Al-Otoom. Preliminary Study of Trace-Cache-Based Control Independence Architecture. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2006. [NCSU library: on-line thesis]
A. A. El-Haj-Mahmoud. Hard-Real-Time Multithreading: A Combined Microarchitectural and Scheduling Approach. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2006. [NCSU library: on-line thesis]
A. V. Anantaraman. Analysis-Managed Processor (AMP): Exceeding the Complexity Limit in Safe-Real-Time Systems. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, April 2006. [NCSU library: on-line thesis]
S. Parthasarathy. Improving Transient Fault Tolerance of Slipstream Processors. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, December 2005. [NCSU library: on-line thesis]
Z. R. Purser. Slipstream Processors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2003. [NCSU library: on-line dissertation]
N. Gupta. Slipstream-Based Steering for Clustered Microarchitectures. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2003. [pdf]
P. S. Ramrakhyani. Dynamic Pipeline Scaling. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2003. [pdf]
A. V. Anantaraman. Reducing Frequency in Real-Time Systems via Speculation and Fall-Back Recovery. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, April 2003. [pdf]
J. J. Koppanalil. A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, May 2002. [pdf]
Patents
E. Rotenberg, R. K. Venkatesan, and A. S. AL-Zawawi. Systems, Methods and Devices for Providing Variable-Latency Write Operations in Memory Devices. US Patent #7,099,215. Filed Feb. 11, 2005. Issued Aug. 29, 2006.
E. Rotenberg and J. Lindsey. Variable-Persistence Molecular Memory Devices and Methods of Operation Thereof. US Patent #6,944,047. Filed Dec. 19, 2002. Issued Sep. 13, 2005.
My Course Projects from UW-Madison
Mark D. Callaghan, Mohammed M. Hoque, and Eric Rotenberg. Level-Two Translation Lookaside Buffers. CS 752: Advanced Computer Architecture I (Prof. M. Hill), Fall Semester 1994. [ps]
Emmanuel Ackaouy and Eric Rotenberg. A Comparison of SCI and Typhoon. CS 757: Advanced Computer Architecture II (Prof. J. Goodman), Spring Semester 1995. [ps]
Eric Rotenberg. An Analytical Model of the SCI Coherence Protocol. CS 747: Advanced Computer System Performance Modeling (Prof. M. Vernon), Spring Semester 1995. [ps]
Quinn Jacobson and Eric Rotenberg. Custom VLSI Design of a Programmable Digital Filter. ECE 755: VLSI Systems Design (Prof. P. Ramanathan), Fall Semester 1995. [ps]
Quinn Jacobson and Eric Rotenberg. Local Instruction Scheduling. CS 701: Programming Languages and Compilers (Prof. C. Fischer), Spring Semester 1996. [ps]
Eric Rotenberg, Paul Thayer, and Jeremy Williamson. Full Shared Memory Support in Blizzard-S. CS 736: Advanced Operating Systems (Prof. Pei Cao), Spring Semester 1996.
Eric Rotenberg. AR-SMT: Coarse-Grain Time Redundancy for High Performance General Purpose Computers. ECE 753: Fault-Tolerant Computing (Prof. K. Saluja), Spring Semester 1998.
- Course project paper (May 14, 1998). [ps]
- Course project talk (May 10, 1998). [ps] Can you find the error in the figure of slide 13?
- This project led to a FTCS-29 conference paper.