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Slipstream Processors 2.0


In this project, we revisit Slipstream Processors, the first leader-follower-style pre-execution microarchitecture, to produce Slipstream Processors 2.0 (SS2). At present, SS2 is the only pre-execution microarchitecture that achieves four key objectives: (1) leader-follower-style pre-execution (easier than per-dynamic-instance helper threads), (2) fully automated in hardware (avoiding risk of compiler-microarchitecture co-dependency), (3) targets both delinquent branches and loads, and (4) overcomes key limitations of closely related microarchitectures (Slipstream 1.0 and Dual Core Execution). Regarding the last item (4), SS2’s key innovation is to remove the forward control-flow slices of delinquent branches and loads, from the leading thread.


Conference and Journal Papers

V. Srinivasan, R. Basu Roy Chowdhury, and E. Rotenberg. Slipstream Processors Revisited: Exploiting Branch Sets. Proceedings of the 47th ACM/IEEE International Symposium on Computer Architecture (ISCA-47), pp. 105-117, May 2020. [pdf]

Student Theses

V. Srinivasan. Slipstream Processors Revisited: Exploiting Branch Sets. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, July 2019. [NCSU library: on-line thesis]


Slipstream Processors Revisited: Exploiting Branch Sets. Presented at ISCA-47 by E. Rotenberg. [pptxvideopdf – lightning talk]


This project is funded by the NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) (NSF grant no. CCF-1823517 and matching Intel grant) and other Intel grants.

Any opinions, findings, and conclusions or recommendations expressed in this website and publications herein are those of the author(s) and do not necessarily reflect the views of the National Science Foundation or Intel Corporation.