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Conference Talks

EXACT: Explicit Dynamic-Branch Prediction with Active Updates. Presented at CF-7 by E. Rotenberg. [pps]

Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. Presented at DSN-37 by V. K. Reddy. [pps]

Transparent Control Independence (TCI). Presented at ISCA-34 by A. S. Al-Zawawi. [pps]

Understanding Prediction-Based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance. Presented at ASPLOS-12 by V. K. Reddy. [pps]

Assertion-Based Microarchitecture Design for Improved Fault Tolerance. Presented at ICCD-24 by V. K. Reddy. [pps]

The State of ZettaRAM. Presented at NANONET-1 by E. Rotenberg. [pps]

Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM. Presented at HPCA-12 by R. K. Venkatesan. [ppt]

Virtual Multiprocessor: An Analyzable, High-Performance Microarchitecture for Real-Time Computing. Presented at CASES’05 by A. El-Haj-Mahmoud. [ppt]

Tapping ZettaRAMTM for Low-Power Memory Systems. Presented at HPCA-11 by R. K. Venkatesan. [ppt]

* The ZettaRAMTM mark is a trademark of ZettaCore Inc.
* The ZettaCoreTM mark is a trademark of ZettaCore Inc.

Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). Presented at RTSS-25 by A. V. Anantaraman. [ppt] [ppt – no animation] [pdf]

Safely Exploiting Multithreaded Processors to Tolerate Memory Latency in Real-Time Systems. Presented at CASES’04 by A. El-Haj-Mahmoud. [ppt] [ppt – no animation] [pdf]

Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. Presented at ISCA-30 by E. Rotenberg. [pdf]

A Case for Dynamic Pipeline Scaling. Presented at CASES’02 by P. Ramrakhyani. [pdf]

Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems. Presented at MICRO-34 by E. Rotenberg. [pdf]

Adaptive Mode Control: A Static-Power-Efficient Cache Design. Presented at PACT’01 by E. Rotenberg. [pdf]

A Study of Slipstream Processors. Presented at MICRO-33 by Z. Purser. [pdf]

Slipstream Processors: Improving both Performance and Fault Tolerance. Presented at ASPLOS-9 by E. Rotenberg. [pdf]

Control Independence in Trace Processors. Presented at MICRO-32 by E. Rotenberg. [pdf]

AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. Presented at FTCS-29 by E. Rotenberg. [pdf]

A Study of Control Independence in Superscalar Processors. Presented at HPCA-5 by E. Rotenberg. [pdf]

Trace Processors. Presented at MICRO-30 by E. Rotenberg. [pdf]

Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. Presented at MICRO-29 by E. Rotenberg. [pdf]

Assigning Confidence to Conditional Branch Predictions. Presented at MICRO-29 by E. Rotenberg. [pdf]

Industry Talks

Other talks to be posted …

Cooperative Redundant Threads (CRT). Presented at IBM-T.J.Watson (July 28, 2000), Compaq-Shrewsbury (July 31, 2000), and Compaq-Marlborough (August 1, 2000). [pdf]

Exploiting Multiple On-Chip Contexts in New Ways. Presented at Intel-MRL (January 2000). [pdf]