Skip to main content

ECE 463/563 Fall 2018 Microprocessor Architecture

DateTopicsNotesReading Assignment
Thurs., Aug. 23Introduction: Overview of class topics, pipelining techniques, defining computer architecturepptx§ 1.1 – 1.4
Tues., Aug. 28Introduction: continued(see Aug. 23 notes)
Thurs., Aug. 30Performance: CPU time equation, benchmarks, summarizing performance, speedup, Amdahl’s Lawpptx§ 1.8 – 1.9
Tues., Sep. 4Performance: Moore’s Law, costs: chip area and power, power metrics(see Aug. 30 notes)§ 1.8 – 1.9, 1.5 – 1.6
Thurs., Sep. 6Caches: Processor-memory perf. gap, temporal and spatial locality, memory hierarchypptx§ 2.1  (also recommended: § 2.2)
Tues., Sep. 11Caches: Cache organization and operation, direct-mapped vs. set-associative vs. fully-associative cachesPart A: pptx
Part B: pptx
§ B.1
Thurs., Sep. 13Caches: Modeling caches generically, replacement policies, LRU, write policies (WBWA, WTNA), victim cachespptx§ B.1
Tues., Sep. 18Caches: Average access time (AAT) equation, optimize three factors affecting AAT, 3C’s model of missespptx§ B.2 – B.3, § 2.1 – 2.3
Thurs., Sep. 20Caches: Techniques for reducing miss rate: block size, size, assoc; hardware and software prefetching; program transformationspptx§ B.3, § 2.1 – 2.3
Tues., Sep. 25Caches: Techniques for reducing miss penalty: L2 cache, victim cache, write buffer, early restart + critical word firstpptx§ B.3, § 2.1 – 2.3
Thurs., Sep. 27Caches: Virtual memory, translation lookaside buffer (TLB), constraints for parallel cache/TLB accesspptx§ B.3 – B.4
Tues., Oct. 2overflow lecture
Thurs., Oct. 4Fall Break
Tues., Oct. 9overflow lecture
Thurs., Oct. 11Midterm Exam
Tues., Oct. 16Pipelining: Work out the steps for executing instructions, design unpipelined datapath, pipelined datapathpptxAppendix C
Thurs., Oct. 18Pipelining: Critical path, cycle time and CPI with/without pipelining, pipeline hazards, structural hazards, control hazardspptx
Appendix C
Tues., Oct. 23Pipelining: Dynamic branch prediction, branch target buffer (BTB), separate BTB+BHT, 1-bit counter, 2-bit counter, global branch history, gselect and gshare predictors, local branch history, Yeh/Patt predictor, hybrid predictorspptx
also: ppt
Appendix C
Thurs., Oct. 25Pipelining: Dynamic branch prediction (cont.)(see Oct. 23 notes)Appendix C
Tues., Oct. 30Pipelining: Dynamic branch prediction (cont.)(see Oct. 23 notes)Appendix C
Thurs., Nov. 1Pipelining: Static branch prediction, delayed branches, data hazards, RAW hazards, eliminating or minimizing stalls due to RAW hazards through data forwarding, load-use stall, WAR and WAW hazards, techniques for mitigating WAR and WAW hazards, data dependencies (true, anti, and output)pptx

Appendix C
Tues., Nov. 6ILP: From in-order to out-of-order: the Issue Queue (IQ); speculation and register renaming: the Reorder Buffer (ROB)pptx§ 3.1, § 3.4
Thurs., Nov. 8ILP: (cont.)
Tues., Nov. 13ILP: (cont.)
Thurs., Nov. 15ILP: (cont.)
Tues., Nov. 20ILP: Precise interrupts, immediate branch misprediction recovery, handling memory dependencies, superscalar complexitypptx
Thurs., Nov. 22Thanksgiving Holiday  
Tues., Nov. 27ILP: (Nov. 20 topics, cont.) 
Thurs., Nov. 29ILP: (Nov. 20 topics, cont.)
Tues., Dec. 4ILP: (Nov. 20 topics, cont.)
Thurs., Dec. 6ILP: VLIW
ISA: What is ISA, impact of ISA choices: CISC vs. RISC, alignment, endian-ness, expressing parallelism in ISA
pptxAppendix A (all sections)