ECE 463/563 Fall 2020 Microprocessor Architecture
| Date | Topics | Notes | Reading Assignment |
|---|---|---|---|
| Mon., Aug. 10 | Introduction: Overview of class topics, pipelining techniques, defining computer architecture Performance: static vs. dynamic instructions; T = (# cycles) x (cycle time); what influences cycles and cycle time | pptx(opens in new window)(opens in new window) | § 1.1 – 1.4 |
| Wed., Aug. 12 | Caches: Processor-memory perf. gap, temporal and spatial locality, memory hierarchy | pptx(opens in new window)(opens in new window) | § 2.1 (also recommended: § 2.2) |
| Mon., Aug. 17 | Caches: Cache organization and operation, direct-mapped vs. set-associative vs. fully-associative caches | Part A: pptx(opens in new window)(opens in new window) Part B: pptx (opens in new window)(opens in new window) | § B.1 |
| Wed., Aug. 19 | Caches: Modeling caches generically, replacement policies, LRU, write policies (WBWA, WTNA) Example L1+L2 simulation (WBWA for both caches) | pptx(opens in new window)(opens in new window) pptx(opens in new window)(opens in new window) | § B.1 |
| Mon., Aug. 24 | continued previous | ||
| Wed., Aug. 26 | continued previous | ||
| Mon., Aug. 31 | classes canceled (NCSU covid-19 move out) pre-recorded modules: victim caches(opens in new window)(opens in new window) write buffers (link to recording to be posted) | pptx(opens in new window)(opens in new window) pptx(opens in new window)(opens in new window) | |
| Wed., Sep. 2 | Caches: 3C’s model of misses | pptx(opens in new window)(opens in new window) | § B.2 – B.3, § 2.1 – 2.3 |
| Mon., Sep. 7 | Caches: Average access time (AAT) equation; impact of cache size, assoc., and block size, on three factors of AAT (and 3C’s misses); impact of adding L2 cache on AAT. | pptx(opens in new window)(opens in new window) | “ |
| Wed., Sep. 9 | Caches: Reducing misses via prefetching and program transformations. | pptx(opens in new window)(opens in new window) | “ |
| Mon., Sep. 14 | Caches: Virtual memory, translation lookaside buffer (TLB), constraints for parallel cache/TLB access. | pptx(opens in new window)(opens in new window) | § B.3 – B.4 |
| Wed., Sep. 16 | Performance: CPU time equation, benchmarks, summarizing performance, speedup, Amdahl’s Law | pptx(opens in new window)(opens in new window) | § 1.8 – 1.9 |
| Mon., Sep. 21 | costs: chip area and power, power metrics pre-recorded modules: chip cost(opens in new window)(opens in new window) power metrics(opens in new window)(opens in new window) | (see Sep. 16 notes) | § 1.8 – 1.9, 1.5 – 1.6 |
| Wed., Sep. 23 | Midterm Exam | ||
| Mon., Sep. 28 | Pipelining: Work out the steps for executing instructions, design unpipelined datapath, pipelined datapath | pptx(opens in new window)(opens in new window) | Appendix C |
| Wed., Sep. 30 | Pipelining: Critical path, cycle time and CPI with/without pipelining, pipeline hazards, structural hazards, control hazards | pptx (opens in new window)(opens in new window) | Appendix C |
| Mon., Oct. 5 | Pipelining: Dynamic branch prediction, branch target buffer (BTB), separate BTB+BHT, 1-bit counter, 2-bit counter, global branch history, gselect and gshare predictors, local branch history, Yeh/Patt predictor, hybrid predictors | pptx(opens in new window)(opens in new window) | Appendix C |
| Wed., Oct. 7 | Pipelining: Dynamic branch prediction (cont.) | (see Oct. 5 notes) | Appendix C |
| Mon., Oct. 12 | Pipelining: Dynamic branch prediction (cont.) | (see Oct. 5 notes) | Appendix C |
| Wed., Oct. 14 | Pipelining: Static branch prediction, delayed branches, data hazards, RAW hazards, eliminating or minimizing stalls due to RAW hazards through data forwarding, load-use stall, WAR and WAW hazards, techniques for mitigating WAR and WAW hazards, data dependencies (true, anti, and output) pre-recorded module: static branch prediction(opens in new window)(opens in new window) | pptx(opens in new window)(opens in new window) pptx(opens in new window)(opens in new window) | Appendix C |
| Mon., Oct. 19 | ILP: From in-order to out-of-order: the Issue Queue (IQ); speculation and register renaming: the Reorder Buffer (ROB) | pptx(opens in new window)(opens in new window) | § 3.1, § 3.4 |
| Wed., Oct. 21 | ILP: (cont.) | ||
| Mon., Oct. 26 | ILP: (cont.) | ||
| Wed., Oct. 28 | ILP: (cont.) | ||
| Mon., Nov. 2 | ILP: Precise interrupts, immediate branch misprediction recovery, handling memory dependencies, superscalar complexity | pptx(opens in new window)(opens in new window) | |
| Wed., Nov. 4 | ILP: (Nov. 2 topics, cont.) | ||
| Mon., Nov. 9 | ILP: (Nov. 2 topics, cont.) | ||
| Wed., Nov. 11 | ILP: (Nov. 2 topics, cont.) | ||
| Mon., Nov. 16 | ILP: VLIW ISA: What is ISA, impact of ISA choices: CISC vs. RISC, alignment, endian-ness, expressing parallelism in ISA | pptx(opens in new window)(opens in new window) | Appendix A (all sections) |